I am experienced in multiple facets of ASIC verification including full-chip simulation, formal, and post-silicon verification (DVT). I have contributed to multiple teams using multiple technologies. I have developed verification plans, test cases, and test components in multiple environments and for multiple teams to develop high-quality, custom ASIC's for the Aruba Networks 6000 and 8000 series of network switches.
Highlights
- Developed standardized performance tests across eight ASIC verification efforts
- Led verification meetings for full-chip testing for an ASIC release cycle
- Created new, reusable verifcation components for multiple unique test cases
- Coordinated with multiple teams to develop full-chip verification test plans
- Formally verified multiple components throughout the ASIC using assertions
- Filed bugs in Jira against designers and followed up on fixes
- Ran, analyzed, and triaged the full-chip simulation tests for seven ASIC release cycles
- Used assertions to formally verify multiple components throughout the ASIC
- Managed my time and assigned tasks through my team's Kanban board