I am experienced in ASIC verification including full and partial chip simulation, formal, and post-silicon verification (DVT). I have contributed to verification efforts using different methodologies. I have developed verification plans, test cases, and test components in multiple verification environments to develop high-quality, custom ASIC's for the Aruba Networking 6000 and 8000 series of network switches.
Highlights
- Wrote standardized performance tests across eight ASIC verification efforts
- Led verification meetings for full-chip testing for an ASIC release cycle
- Wrote new, reusable verification components for unique test cases
- Wrote assertion-based verification test benches
- Debugged failing tests in order to file a bug or fix the environment
- Reproduced bugs found in post-silicon in pre-silicon tests
- Coordinated with international teams to develop full-chip verification test plans
- Filed bugs in Jira against designers and followed up on fixes
- Ran and debugged the full-chip simulation tests for seven ASIC release cycles